Large scale integrated circuit systems have been developed for performing a variety of circuit functions in conjunction with different types of input and output devices. Situations exist where one manufacturer of systems incorporating such integrated circuit devices utilizes an external crystal oscillator as a source of clock inputs for the system. When such an external crystal oscillator clock is employed, the feedback loop for the clock is interconnected between two different output terminals or pins on the circuit which is to be driven by the clock. In other situations, however, a different source of clock signals is employed which is connected to only one of these pins, and the other pin is connected directly to a fixed potential, which typically is VDD or VSS.
Clearly, if the internal clock interface circuit portion of the integrated circuit to which the system device pins are connected is configured for one or the other of these possible clock signal input connections, it will not operate properly if the other clock signal input connection is used. For example, if the internal circuitry of the chip for distributing the clock signals to other components of the integrated circuit is configured with interconnections to the bonding pads connected to the output pins for operating in the feedback loop of a crystal oscillator clock, the tying of one or the other of these pins to a constant potential, will prevent the clock signals from being recognized or utilized within the internal circuit of the chip. The converse also is true. If the internal configuration of the clock pulse distribution circuit is made to function properly with a source of clock signals connected to a single terminal, with the other of two output pins tied to a fixed potential, the interconnection of a crystal oscillator feedback loop across the two pins will result in failure of operation of the system.
In the past, it has been necessary to configure the interface circuit between the clock input pins and the internal circuit of the chip, specifically for the type of clock input signal source which is to be used with the system. As mentioned above, if the clock interface circuit is configured for one type of clock input, it will not function properly for another type of clock input.
It is desirable to provide a clock input interface circuit which automatically identifies the external clock connected to the input pins, and which automatically self-configures to provide a proper clock signal to the remainder of the circuit with which the interface is used.